As integrated circuits continue to develop, they continue to have higher device densities and clocking rates. As a result, it requires ever-increasing numbers of test vectors to properly test them, which in turn requires larger and larger amounts of tester vector memory. Still further, manufacturing newer integrated circuits requires even more complex manufacturing techniques, with the corresponding increase in problems and costs related to the production of integrated circuits. To address these problems, and to allow for a self-test of integrated circuits in the field, a testing technique referred to as “built-in self-test” (BIST) is expected to be used more and more in the future.
With logic built-in self-test (LBIST), test circuits for testing the functional logic of an integrated circuit are added to the circuit's design. FIG. 1 illustrates the general configuration of an integrated circuit using LBIST. As seen in this figure, an integrated circuit 101 includes a test stimulus generator 103, a circuit-under-test (CUT) 105, and a test response evaluator 107. The integrated circuit 101 also includes a test control module 109, for controlling the operation of the test stimulus generator 103, the circuit-under-test (CUT) 105, and the test response evaluator 107. With this arrangement, the test stimulus generator 103 generates test stimuli that are applied to the circuit-under-test 105 through scan chains. The scan chains may be, for example, flip-flops in the circuit-under-test 105 that can be configured into serial shift registers during a test mode.
The self-test is performed by repeatedly shifting the generated test stimuli into the scan chains so that they are applied to the circuit-under-test 105, and operating the circuit-under-test 105 for a number of clock cycles in its functional application mode. Various techniques for generating efficient stimuli are well-known in the art. These include, for example, techniques for generating test stimuli for built-in self-test applications that improve the random testability of the circuit by state-of-the-art test points insertion (TPI), by a linear feedback shift register (LFSR) reseeding, by Bit-Flipping-Logic (see, for example, U.S. Pat. No. 6,789,221, issued Sep. 7, 2004, which patent is incorporated entirely herein by reference), or by a cycle-based stimuli generation (see, for example, European Patent Application No. 06126627.6, filed on Dec. 20, 2006, which application is incorporated entirely herein by reference as well).
The responses produced by the circuit-under-test 105 are captured by the scan chains, and relayed to the test response evaluator 107 where, for example, they are compacted on-chip using a compacting device, such as a multiple input shift register (MISR), to produce a compacted test signature. The compacted test signature can then be compared against a corresponding fault-free signature to determine if the integrated circuit has any of the faults tested for by the test stimuli. Depending upon the implementation, the compacted test signature can be compared with the fault-free signature on-chip, or after it has been exported off of the integrated circuit for comparison by, for example, automated test equipment.
While the responses produced by the circuit-under-test 105 include data bits that have known good circuit response data and which can detect a fault, the responses also may contain “unknown” data values (that is, data values that cannot be predicted because they may vary from test to test). If these unknown data values (referred to herein as “X values” or “Xs”) are compacted with the relevant data values, then the compacted test signature may not contain enough stable and predictable information to determine if the integrated circuit has one or more of the targeted faults.
The most common technique to get avoid the occurrence of X values in logic-BIST is referred to as “X bounding.” With this technique, the circuit-under-test is modified to prevent noted X values from occurring. This technique has a significant disadvantage, however, in that the functional core logic has to be changed, which might impact the timing of the core. An alternative technique to avoid the effect of X values is to add some logic to mask out the X values after they have been output from the core logic, a technique sometimes referred to as “X-masking.” This masking technique is typically used in conventional test response compression techniques, such as, for example, the compression techniques provided by the Mentor Graphics TestKompress electronic design automation (EDA) tools available from Mentor Graphics Corporation of Wilsonville, Oreg. (It should be appreciated that, as used herein, the term “conventional” may include built-in self-test compression techniques that are employed in the integrated circuit manufacturing industry, but may nonetheless be proprietary and maintained in secret, and thus not be publicly known.)
With these conventional compression techniques, however, the test response values from the core logic are masked based upon masking information that is imported from off of the integrated circuit being tested. More particularly, with conventional compression techniques, the masking circuitry is controlled based upon masking data that must be provided from outside of the integrated circuit being tested. Typically, this masking data must be provided by a separate, external testing device, requiring the use of such a device to complete a built-in self-test operation.